counter Entity Reference

Counter-Component. More...

Collaboration diagram for counter:

Libraries
ieee
	Use Standard Library.

Use Clauses
std_logic_1164
	Use Logic Elements.

Generics
divider	INTEGER
	Prescaler for PWM-signal.

Ports
clock	in STD_LOGIC
	input clock
reset_n	in STD_LOGIC
	global reset
enable	in STD_LOGIC
	enables component
clk_out	out STD_LOGIC
	divided clock output

Detailed Description

Counter-Component.

Definition at line 29 of file counter.vhd.

Member Data Documentation

divider INTEGER

Generic

Prescaler for PWM-signal.

For this purpose 2,5 ms are used as minimal pulse-width.

The prescaler is calculated with the given and desired frequency via the following formula:

\begin{equation*} \text{prescaler} = \frac{f_{\text{clock}} \text{Hz}}{f_{\text{prescaler}} \text{Hz}} \end{equation*}

e.g.:

\begin{equation*} \left.\begin{aligned} f_{\text{prescaler}} &= \frac{5}{2}\,\text{ms} \newline &= 400\,\text{Hz} \newline\newline \text{prescaler} &= \frac{50\,\text{Mhz}}{400\,\text{Hz}} \newline &= 125000 \newline \end{aligned} \right\} \qquad \text{pulse-width: 2.5 ms} \end{equation*}

For simulation-purpose the divider was set to 125 for faster wave generation.

Definition at line 52 of file counter.vhd.

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The documentation for this class was generated from the following file:

• counter.vhd