Stepper-Motor-Control  v3.0.0
System on a Chip 2014 - Group 04
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interface_RTX_Base.vhd
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1 -------------------------------------------------------------------------------
2 --! @file interface_RTX_Base.vhd
3 --! @author Michael Riedel
4 --! @author Marc Kossmann
5 --! @version v1.0.0
6 --! @date 11.11.2014
7 --! @brief Interface Base-File (RTX) to embed Qsys-outputAssignments->))
8 --!
9 --! @par History:
10 --! @details v0.1.0 28.10.2014 Kossmann
11 --! - initial setup
12 --! @details v1.0.0 03.11.2014 Riedel
13 --! - corrected documentation and indention
14 --! @details v1.0.1 05.11.2014 Riedel
15 --! - renamed led-outputs in StepperMotorControl-Component
16 --! - removed unused-comments and corrected formatting
17 -------------------------------------------------------------------------------
18 
19 --! Use Standard Library
20 LIBRARY ieee;
21 --! Use Logic Elements
22 USE ieee.std_logic_1164.all;
23 
24 --! Use Work Library
25 LIBRARY work;
26 
27 
28 --! @brief Base-Entity. This Entity describes the connection
29 --! to DE2-Board
31  PORT
32  (
33  CLOCK_50_B5B : IN STD_LOGIC; --! 50 MHz Oscillator
34  CPU_RESET_n : IN STD_LOGIC; --! CPU reset_n
35  SRAM_A : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); --! SRAM address lines
36  SRAM_D : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! SRAM-data bus
37  SRAM_CE_N : OUT STD_LOGIC; --! SRAM chip enable
38  SRAM_LB_N : OUT STD_LOGIC; --! SRAM lower byte line
39  SRAM_OE_N : OUT STD_LOGIC; --! SRAM output enable (read) line
40  SRAM_UB_N : OUT STD_LOGIC; --! SRAM upper byte linkage
41  SRAM_WE_N : OUT STD_LOGIC; --! SRAM write enable line
42  KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --! key-definition
43  SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0); --! slidINg switches
44  LED9 : OUT STD_LOGIC; --! debug LEDs
45  LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --! green leds
46  LEDR : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --! red leds
47  HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --! HEX display 0
48  HEX1 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --! HEX display 1
49  HEX2 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --! HEX display 2
50  HEX3 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --! HEX display 3
51  LCD_RS : OUT STD_LOGIC; --! LCD RS
52  LCD_RW : OUT STD_LOGIC; --! LCD RW
53  LCD_DQ : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); --! LCD data
54  LCD_EN : OUT STD_LOGIC; --! LCD enable
55  HSMC_RX_P : OUT STD_LOGIC_VECTOR(16 DOWNTO 0); --! Motor_pwm1( bit 0 ) and Motor_pwm2( bit 1 )
56  HSMC_RX_N : OUT STD_LOGIC_VECTOR(16 DOWNTO 0); --! Motor_pwm3( bit 0 ) and Motor_pwm4( bit 1 )
57  HSMC_TX_N : OUT STD_LOGIC_VECTOR(16 DOWNTO 0); --! Motor_en_a( bit 2 )
58  HSMC_TX_P : OUT STD_LOGIC_VECTOR(16 DOWNTO 0) --! Motor_en_b( bit 3 )
59  );
60 END interface_RTX_Base;
61 
62 --! @brief NIOS-Processor with SOPC-Peripherals
63 ARCHITECTURE a1 OF interface_RTX_Base IS
64 
65 COMPONENT StepperMotorControl IS
66  PORT
67  (
68  reset_reset_n : IN STD_LOGIC := '0';
69  clk_clk : IN STD_LOGIC := '0';
70  sram_SRAM_OE_N : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
71  sram_SRAM_CE_N : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
72  sram_SRAM_BE_N : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
73  sram_SRAM_D : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
74  sram_SRAM_A : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
75  sram_SRAM_WE_N : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
76  sw_export : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
77  lcd_RS : OUT STD_LOGIC;
78  lcd_RW : OUT STD_LOGIC;
79  lcd_data : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
80  lcd_E : OUT STD_LOGIC;
81  key_export : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
82  hex0_export : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
83  hex1_export : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
84  hex2_export : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
85  hex3_export : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
86  led9_export : OUT STD_LOGIC;
87  registers_conduit_nios_redleds : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
88  registers_conduit_nios_greenleds : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
89  mcu_conduit_motor_motor_pwm : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
90  mcu_conduit_motor_motor_en : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
91  );
92 END COMPONENT StepperMotorControl;
93 
94 SIGNAL be_n : STD_LOGIC_VECTOR(1 DOWNTO 0); --! Byte enable signals
95 SIGNAL motor_pwm_wire : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL motor_en_wire : STD_LOGIC_VECTOR(1 DOWNTO 0);
97 
98 BEGIN
99  -- RAM
100  SRAM_LB_N <= be_n(0);
101  SRAM_UB_N <= be_n(1);
102 
103  -- Motor PWM
104  HSMC_RX_P(0) <= motor_pwm_wire(0);
105  HSMC_RX_P(1) <= motor_pwm_wire(1);
106  HSMC_RX_N(0) <= motor_pwm_wire(2);
107  HSMC_RX_N(1) <= motor_pwm_wire(3);
108  -- visualized
109  LEDG(3) <= motor_pwm_wire(3);
110  LEDG(2) <= motor_pwm_wire(1);
111  LEDG(1) <= motor_pwm_wire(2);
112  LEDG(0) <= motor_pwm_wire(0);
113 
114  -- Motor EN
115  HSMC_TX_N(2) <= motor_en_wire(0);
116  HSMC_TX_P(3) <= motor_en_wire(1);
117  -- visualized
118  LEDG(5 DOWNTO 4) <= motor_en_wire;
119 
120  u0 : COMPONENT StepperMotorControl
121  PORT MAP
122  (
123  reset_reset_n => CPU_RESET_n,
124  clk_clk => CLOCK_50_B5B,
125  sram_SRAM_OE_N(0) => SRAM_OE_N,
126  sram_SRAM_CE_N(0) => SRAM_CE_N,
127  sram_SRAM_BE_N => be_n,
128  sram_SRAM_D => SRAM_D,
129  sram_SRAM_A(18 DOWNTO 1) => SRAM_A ,
130  sram_SRAM_WE_N(0) => SRAM_WE_N,
131  sw_export => SW,
132  lcd_RS => LCD_RS,
133  lcd_RW => LCD_RW,
134  lcd_data => LCD_DQ,
135  lcd_E => LCD_EN,
136  key_export => KEY,
137  hex0_export => HEX0,
138  hex1_export => HEX1,
139  hex2_export => HEX2,
140  hex3_export => HEX3,
141  led9_export => LED9,
142  registers_conduit_nios_redleds => LEDR,
143  --registers_conduit_nios_greenleds => LEDG
144  mcu_conduit_motor_motor_pwm => motor_pwm_wire,
145  mcu_conduit_motor_motor_en => motor_en_wire
146  );
147 END a1;
out HSMC_TX_PSTD_LOGIC_VECTOR(16 DOWNTO0)
Motor_en_b( bit 3 )
in CPU_RESET_nSTD_LOGIC
CPU reset_n.
in KEYSTD_LOGIC_VECTOR(3 DOWNTO0)
key-definition
inout SRAM_DSTD_LOGIC_VECTOR(15 DOWNTO0)
SRAM-data bus.
out HSMC_RX_PSTD_LOGIC_VECTOR(16 DOWNTO0)
Motor_pwm1( bit 0 ) and Motor_pwm2( bit 1 )
out LEDRSTD_LOGIC_VECTOR(7 DOWNTO0)
red leds
out HEX0STD_LOGIC_VECTOR(6 DOWNTO0)
HEX display 0.
out SRAM_UB_NSTD_LOGIC
SRAM upper byte linkage.
in SWSTD_LOGIC_VECTOR(9 DOWNTO0)
slidINg switches
out LED9STD_LOGIC
debug LEDs
_library_ ieeeieee
Use Standard Library.
Base-Entity. This Entity describes the connection to DE2-Board.
out HSMC_TX_NSTD_LOGIC_VECTOR(16 DOWNTO0)
Motor_en_a( bit 2 )
out LCD_RSSTD_LOGIC
LCD RS.
out HEX3STD_LOGIC_VECTOR(6 DOWNTO0)
HEX display 3.
out HEX1STD_LOGIC_VECTOR(6 DOWNTO0)
HEX display 1.
out SRAM_CE_NSTD_LOGIC
SRAM chip enable.
out LEDGSTD_LOGIC_VECTOR(7 DOWNTO0)
green leds
out SRAM_WE_NSTD_LOGIC
SRAM write enable line.
out LCD_ENSTD_LOGIC
LCD enable.
out LCD_RWSTD_LOGIC
LCD RW.
out SRAM_ASTD_LOGIC_VECTOR(17 DOWNTO0)
SRAM address lines.
out SRAM_LB_NSTD_LOGIC
SRAM lower byte line.
out HSMC_RX_NSTD_LOGIC_VECTOR(16 DOWNTO0)
Motor_pwm3( bit 0 ) and Motor_pwm4( bit 1 )
out HEX2STD_LOGIC_VECTOR(6 DOWNTO0)
HEX display 2.
inout LCD_DQSTD_LOGIC_VECTOR(7 DOWNTO0):=(others=> '0')
LCD data.
out SRAM_OE_NSTD_LOGIC
SRAM output enable (read) line.
in CLOCK_50_B5BSTD_LOGIC
50 MHz Oscillator