1 -----------------------------------------------------------------------------
2 --! @file register_interface_tb.vhd
3 --! @author Marc Kossmann
4 --! @author Michael Riedel
8 --! @brief Testbench for Register Component
9 --! @details Tests full functionality of component
11 --! @details v0.1.0 06.11.2014 Kossmann
13 --! @details v0.1.1 07.11.2014 Kossmann
14 --! - finished reset_n task
15 --! @details v1.0.0 18.11.2014 Riedel & Kossmann
16 --! - verified functionality -> release MS2
17 --! @details v1.0.1 23.11.2014 Riedel & Kossmann
18 --! - added test of reserved mode
19 --! @details v2.0.0 05.12.2014 Riedel & Kossmann
20 --! - release milestone 3b
21 -----------------------------------------------------------------------------
23 --! Use Standard Library
25 --! Use Logic Elements
26 USE ieee.std_logic_1164.
all;
27 --! Use Conversion Functions
28 USE ieee.STD_LOGIC_SIGNED.
all;
30 --! @brief Entity of testbench for register_interface
34 --! @brief Architecture of testbench for register_interface
35 --! @details first test if all registers can be written
36 --! then resets everything
37 --! test if set and clear is working the right way
39 SIGNAL write_n : := '1';
40 SIGNAL greenleds : (7 DOWNTO 0) := (OTHERS => '0');
41 SIGNAL addr : (2 DOWNTO 0) := "111";
42 SIGNAL clock : := '0';
44 SIGNAL reset_n : := '0';
45 SIGNAL read_n : := '1';
46 SIGNAL redleds : (7 DOWNTO 0) := (OTHERS => '0');
47 SIGNAL write_data : (31 DOWNTO 0) := (OTHERS => '0');
49 SIGNAL read_data : (31 DOWNTO 0) := (OTHERS => '0');
51 SIGNAL direction : := '0';
52 SIGNAL mode : (3 DOWNTO 0) := (OTHERS => '0');
53 SIGNAL speed : (2 DOWNTO 0) := (OTHERS => '0');
54 SIGNAL steps : (31 DOWNTO 0) := (OTHERS => '0');
59 clock :
IN ;
--! Avalon clock
60 reset_n :
IN ;
--! Avalon reset the component
61 ce_n :
IN ;
--! Avalon chip enable
62 read_n :
IN ;
--! Avalon set read-request
63 write_n :
IN ;
--! Avalon set write-request
64 addr :
IN (
2 DOWNTO 0);
--! Avalon address bus (selects the register)
65 write_data :
IN (
31 DOWNTO 0);
--! Avalon write data to selected register
66 read_data :
OUT (
31 DOWNTO 0);
--! Avalon read data from selected register
67 irq :
OUT ;
--! Avalon IRQ line
68 greenleds :
OUT (
7 DOWNTO 0);
--! external: green leds
69 redleds :
OUT (
7 DOWNTO 0);
--! external: red leds
70 run :
OUT ;
--! enable signal for mcu
71 direction :
OUT ;
--! direction signal for mcu
72 mode :
OUT (
3 DOWNTO 0);
--! output of Mode bits for mcu
73 speed :
OUT (
2 DOWNTO 0);
--! output of speedReg for mcu
74 steps :
IN (
31 DOWNTO 0);
--! input for stepsReg for mcu
75 ir :
IN --! input request of mcu
101 -- first test if all registers can be written
102 -- then resets everything
103 -- test if set and clear is working the right way
104 clock <= not clock after 10 ns;
105 ce_n <= '0' after 20 ns;
106 reset_n <= '1' after 20 ns,
109 write_n <= '0' after 30 ns;
110 read_n <= '0' after 30 ns;
111 addr <= "000" after 30 ns, -- ctrlReg
112 "001" after 50 ns, -- ctrlSetReg
113 "010" after 70 ns, -- ctrlClrReg
114 "011" after 90 ns, -- speedReg
115 "100" after 110 ns, -- stepsReg
116 -- reset; now testing set and clear functionality
117 "000" after 150 ns, -- ctrlReg
118 "001" after 170 ns, -- ctrlSetReg
119 "010" after 190 ns, -- ctrlClrReg
120 "000" after 200 ns, -- ctrlReg
121 "111" after 230 ns;
-- reserved
122 write_data(7 downto 0) <= "11111111" after 30 ns,
123 "10101010" after 150 ns,
124 "01010101" after 170 ns,
125 "10101010" after 190 ns,
126 "00000000" after 210 ns;
127 steps(15 downto 8) <= "11111111" after 130 ns;
128 ir <= '1' after 130 ns;
130 finish_sim_time :
process
134 report "simulation finished"
136 end process finish_sim_time;
in ce_nSTD_LOGIC
Avalon chip enable.
in read_nSTD_LOGIC
Avalon set read-request.
out redledsSTD_LOGIC_VECTOR(7 DOWNTO0)
external: red leds
Entity of testbench for register_interface.
Register Interface-Component.
in write_nSTD_LOGIC
Avalon set write-request.
out runSTD_LOGIC
enable signal for mcu
_library_ ieeeieee
Use Standard Library.
out speedSTD_LOGIC_VECTOR(2 DOWNTO0)
output of speedReg for mcu
in addrSTD_LOGIC_VECTOR(2 DOWNTO0)
Avalon address bus (selects the register)
out irqSTD_LOGIC
Avalon IRQ line.
out read_dataSTD_LOGIC_VECTOR(31 DOWNTO0)
Avalon read data from selected register.
in reset_nSTD_LOGIC
Avalon reset the component.
out greenledsSTD_LOGIC_VECTOR(7 DOWNTO0)
external: green leds
in write_dataSTD_LOGIC_VECTOR(31 DOWNTO0)
Avalon write data to selected register.
in clockSTD_LOGIC
Avalon clock.
in stepsSTD_LOGIC_VECTOR(31 DOWNTO0)
input for stepsReg for mcu
out directionSTD_LOGIC
direction signal for mcu
in irSTD_LOGIC
input request of mcu
out modeSTD_LOGIC_VECTOR(3 DOWNTO0)
output of Mode bits for mcu