Stepper-Motor-Control  v3.0.0
System on a Chip 2014 - Group 04
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milestone3_tb.vhd
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1 -------------------------------------------------------------------------------
2 --! @file milestone3_tb.vhd
3 --! @author Marc Kossmann
4 --! @author Michael Riedel
5 --! @version v1.0.0
6 --! @date 05.12.2014
7 --!
8 --! @brief Testbench for Milestone 3
9 --! @details Tests the bahavior when all components are wired together
10 --! @par History:
11 --! @details v0.1.0 02.12.2014 Kossmann
12 --! - first draft
13 --! @details v0.1.1 04.12.2014 Riedel
14 --! - corrected output-naming for LEDs
15 --! - corrected formatting and indention
16 --! @details v1.0.0 05.12.2014 Riedel & Kossmann
17 --! - release milestone 3b
18 -------------------------------------------------------------------------------
19 
20 --! Use Standard Library
21 LIBRARY ieee;
22 --! Use Logic Elements
23 USE ieee.STD_LOGIC_1164.all;
24 --! Use Arithmetic Functions
25 USE ieee.STD_LOGIC_arith.all;
26 --! Use Conversion Functions
27 USE ieee.STD_LOGIC_SIGNED.all;
28 
29 --! @brief Entity of testbench for milestone3
30 ENTITY milestone3_tb IS
31  GENERIC
32  (
33  --! @brief Prescaler for PWM-signal.
34  --! @details For this purpose 2,5 ms are used as minimal pulse-width.
35  --! @details The prescaler is calculated with the given and desired frequency
36  --! via the following formula:
37  --! \f{equation*}{
38  --! \text{prescaler} = \frac{f_{\text{clock}} \text{Hz}}{f_{\text{prescaler}} \text{Hz}}
39  --! \f}
40  --! e.g.:
41  --! \f{equation*}{
42  --! \left.\begin{aligned}
43  --! f_{\text{prescaler}} &= \frac{5}{2}\,\text{ms} \newline
44  --! &= 400\,\text{Hz} \newline\newline
45  --! \text{prescaler} &= \frac{50\,\text{Mhz}}{400\,\text{Hz}} \newline
46  --! &= 125000 \newline
47  --! \end{aligned}
48  --! \right\}
49  --! \qquad \text{pulse-width: 2.5 ms}
50  --! \f}
51  --! @details For simulation-purpose the divider was set to 125 for faster wave generation.
52  divider : INTEGER := 125
53  );
54 END;
55 
56 --! @brief Architecture of testbench for milestone3
57 ARCHITECTURE milestone3_tb_arch OF milestone3_tb IS
58 
59  SIGNAL LEDG : STD_LOGIC_VECTOR (7 DOWNTO 0) := (others => '0');
60  SIGNAL CLOCK_50_B5B : STD_LOGIC := '0';
61  SIGNAL HSMC_TX_P : STD_LOGIC_VECTOR (16 DOWNTO 0) := (others => '0');
62  SIGNAL HSMC_RX_N : STD_LOGIC_VECTOR (16 DOWNTO 0) := (others => '0');
63  SIGNAL KEY : STD_LOGIC_VECTOR (3 DOWNTO 0) := (others => '1'); -- low active
64  SIGNAL SW : STD_LOGIC_VECTOR (9 DOWNTO 0) := (others => '0');
65  SIGNAL LEDR : STD_LOGIC_VECTOR (7 DOWNTO 0) := (others => '0');
66  SIGNAL HSMC_TX_N : STD_LOGIC_VECTOR (16 DOWNTO 0) := (others => '0');
67  SIGNAL HSMC_RX_P : STD_LOGIC_VECTOR (16 DOWNTO 0) := (others => '0');
68  SIGNAL CPU_RESET_n : STD_LOGIC := '0';
69  COMPONENT milestone3
70  GENERIC
71  (
72  divider : INTEGER
73  );
74  PORT (
75  LEDG : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
76  CLOCK_50_B5B : IN STD_LOGIC;
77  HSMC_TX_P : OUT STD_LOGIC_VECTOR (16 DOWNTO 0);
78  HSMC_RX_N : OUT STD_LOGIC_VECTOR (16 DOWNTO 0);
79  KEY : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
80  SW : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
81  LEDR : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
82  HSMC_TX_N : OUT STD_LOGIC_VECTOR (16 DOWNTO 0);
83  HSMC_RX_P : OUT STD_LOGIC_VECTOR (16 DOWNTO 0);
84  CPU_RESET_n : IN STD_LOGIC );
85  END COMPONENT;
86 BEGIN
87  DUT : milestone3
88  GENERIC MAP
89  (
90  divider => divider
91  )
92  PORT MAP
93  (
94  LEDG => LEDG,
95  CLOCK_50_B5B => CLOCK_50_B5B,
96  HSMC_TX_P => HSMC_TX_P,
97  HSMC_RX_N => HSMC_RX_N,
98  KEY => KEY,
99  SW => SW,
100  LEDR => LEDR,
101  HSMC_TX_N => HSMC_TX_N,
102  HSMC_RX_P => HSMC_RX_P,
103  CPU_RESET_n => CPU_RESET_n
104  );
105 
106  -- creates the clock
107  CLOCK_50_B5B <= not CLOCK_50_B5B AFTER 10 ns;
108  -- initial reset
109  CPU_RESET_n <= '0', '1' AFTER 20 ns;
110 
111  --Basic functionality
112  --Testing continous run with speed 7.
113  --750 us simtime
114 -- sw(1) <= '0'; --direction ('0' is left)
115 -- sw(5 DOWNTO 2) <= "0001"; --mode
116 -- sw(6) <= '1'; --interrupt enabled
117 -- sw(9 DOWNTO 7) <= "111"; --speed
118 -- -- low active key
119 -- key(0) <= '0' AFTER 100 ns, --on
120 -- '1' AFTER 130 ns;
121 
122  --Testing continous run with speed 7 and 6. Run/stop switched
123  --750 us simtime
124 -- sw(1) <= '0'; --direction ('0' is left)
125 -- sw(5 DOWNTO 2) <= "0001"; --mode
126 -- sw(6) <= '1'; --interrupt enabled
127 -- sw(9 DOWNTO 7) <= "111", --speed
128 -- "110" AFTER 200 us;
129 -- -- low active key
130 -- key(0) <= '0' AFTER 100 ns, --on
131 -- '1' AFTER 130 ns,
132 -- '0' AFTER 300 us, --off
133 -- '1' AFTER 301 us,
134 -- '0' AFTER 400 us, --on
135 -- '1' AFTER 401 us;
136 
137  --Testing Chain of Steps 1/4 with speed 7. Direction switched and restart
138  --1050 us simtime
139 -- sw(1) <= '0', --direction ('0' is left)
140 -- '1' AFTER 300 us;
141 -- sw(5 DOWNTO 2) <= "0010"; --mode
142 -- sw(6) <= '1'; --interrupt enabled
143 -- sw(9 DOWNTO 7) <= "111"; --speed
144 -- key(0) <= '0' AFTER 100 ns, -- low active
145 -- '1' AFTER 130 ns;
146 
147  --Testing Chain of Steps 1/2 with speed 7. Direction switched
148  --1100 us simtime
149  --sw(1) <= '0', --direction ('0' is left)
150 -- '1' AFTER 300 us;
151 -- sw(5 DOWNTO 2) <= "0110"; --mode
152 -- sw(6) <= '1'; --interrupt enabled
153 -- sw(9 DOWNTO 7) <= "111"; --speed
154 -- key(0) <= '0' AFTER 100 ns, -- low active
155 -- '1' AFTER 130 ns,
156 -- '0' AFTER 550 us, --on
157 -- '1' AFTER 551 us;
158 
159  -- Testing CoS 1/4 after finish CoS 1/2 with speed = 7, direction = left
160  -- 3000 us sim time for both
161  sw(1) <= '0'; --direction ('0' is left)
162  sw(5 DOWNTO 2) <= "0010", --mode
163  "0110" after 1200 us;
164  sw(6) <= '1'; --interrupt enabled
165  sw(9 DOWNTO 7) <= "111"; --speed
166  key(0) <= '0' AFTER 100 ns, -- on
167  '1' AFTER 130 ns,
168  '0' AFTER 1250 us, -- off
169  '1' AFTER 1251 us,
170  '0' AFTER 1350 us, -- on
171  '1' AFTER 1351 us;
172 
173  -- Testing CoS 1/2 multiple times with speed = 7, direction = left
174  -- 4000 us sim time for both
175 -- sw(1) <= '0'; --direction ('0' is left)
176 -- sw(5 DOWNTO 2) <= "0110"; --mode
177 -- sw(6) <= '1'; --interrupt enabled
178 -- sw(9 DOWNTO 7) <= "111"; --speed
179 -- key(0) <= '0' AFTER 100 ns, -- on
180 -- '1' AFTER 130 ns,
181 -- '0' AFTER 1050 us, -- off
182 -- '1' AFTER 1051 us,
183 -- '0' AFTER 2200 us, -- on
184 -- '1' AFTER 2201 us,
185 -- '0' AFTER 3400 us, -- off
186 -- '1' AFTER 3401 us;
187 
188 END;
milestone3.HSMC_RX_P
out HSMC_RX_PSTD_LOGIC_VECTOR(16 DOWNTO0)
Motor_pwm1( bit 0 ) and Motor_pwm2( bit 1 )
Definition: milestone3.vhd:64
milestone3_tb
Entity of testbench for milestone3.
Definition: milestone3_tb.vhd:30
milestone3.LEDR
out LEDRSTD_LOGIC_VECTOR(7 DOWNTO0)
red leds
Definition: milestone3.vhd:70
milestone3_tb.divider
dividerINTEGER:=125
Prescaler for PWM-signal.
Definition: milestone3_tb.vhd:53
milestone3
Milestone 3.
Definition: milestone3.vhd:35
milestone3.divider
dividerinteger:=125000
Prescaler for PWM-signal.
Definition: milestone3.vhd:58
milestone3.CPU_RESET_n
in CPU_RESET_nSTD_LOGIC
resets the component
Definition: milestone3.vhd:61
milestone3.LEDG
out LEDGSTD_LOGIC_VECTOR(7 DOWNTO0)
green leds
Definition: milestone3.vhd:68
milestone3.SW
in SWSTD_LOGIC_VECTOR(9 DOWNTO0)
switch input
Definition: milestone3.vhd:62
milestone3.HSMC_TX_P
out HSMC_TX_PSTD_LOGIC_VECTOR(16 DOWNTO0)
Motor_en_b( bit 3 )
Definition: milestone3.vhd:67
milestone3.CLOCK_50_B5B
in CLOCK_50_B5BSTD_LOGIC
component clock
Definition: milestone3.vhd:60
milestone3.HSMC_TX_N
out HSMC_TX_NSTD_LOGIC_VECTOR(16 DOWNTO0)
Motor_en_a( bit 2 )
Definition: milestone3.vhd:66
milestone3.KEY
in KEYSTD_LOGIC_VECTOR(3 DOWNTO0)
key input
Definition: milestone3.vhd:63
milestone3.HSMC_RX_N
out HSMC_RX_NSTD_LOGIC_VECTOR(16 DOWNTO0)
Motor_pwm3( bit 0 ) and Motor_pwm4( bit 1 )
Definition: milestone3.vhd:65
milestone3.ieee
_library_ ieeeieee
Use Standard Library.
Definition: milestone3.vhd:30